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CY8C27143, CY8C27243 CY8C27443, CY8C27543, CY8C27643
PSoC(R) Programmable System-on-ChipTM
Features

Powerful Harvard Architecture Processor M8C Processor Speeds to 24 MHz 8x8 Multiply, 32-Bit Accumulate Low Power at High Speed 3.0 to 5.25V Operating Voltage Operating Voltages Down to 1.0V Using On-Chip Switch Mode Pump (SMP) Industrial Temperature Range: -40C to +85C Advanced Peripherals (PSoC(R) Blocks) 12 Rail-to-Rail Analog PSoC Blocks Provide: * Up to 14-Bit ADCs * Up to 9-Bit DACs * Programmable Gain Amplifiers * Programmable Filters and Comparators 8 Digital PSoC Blocks Provide: * 8- to 32-Bit Timers, Counters, and PWMs * CRC and PRS Modules * Up to 2 Full-Duplex UARTs * Multiple SPITM Masters or Slaves * Connectable to all GPIO Pins Complex Peripherals by Combining Blocks Precision, Programmable Clocking Internal 2.5% 24/48 MHz Oscillator 24/48 MHz with Optional 32 kHz Crystal Optional External Oscillator, up to 24 MHz Internal Oscillator for Watchdog and Sleep Flexible On-Chip Memory 16K Flash Program Storage 50,000 Erase/Write Cycles 256 Bytes SRAM Data Storage In-System Serial Programming (ISSP) Partial Flash Updates Flexible Protection Modes EEPROM Emulation in Flash Programmable Pin Configurations a. 25 mA Sink on all GPIO b. Pull up, Pull down, High Z, Strong, or Open Drain Drive Modes on all GPIO c. Up to 12 Analog Inputs on GPIO d. Four 30 mA Analog Outputs on GPIO e. Configurable Interrupt on all GPIO
Additional System Resources I2C Slave, Master, and Multi-Master to 400 kHz Watchdog and Sleep Timers User-Configurable Low Voltage Detection Integrated Supervisory Circuit On-Chip Precision Voltage Reference Complete Development Tools Free Development Software (PSoC DesignerTM) Full Featured, In-Circuit Emulator and Programmer Full Speed Emulation Complex Breakpoint Structure 128K Trace Memory
Logic Block Diagram
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
PSoC CORE
System Bus
Global Digital Interconnect SRAM 256 Bytes Interrupt Controller
Analog Drivers
Global Analog Interconnect Flash 16K Sleep and Watchdog
SROM
CPUCore (M8C)
Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital Block Array
ANALOG SYSTEM
Analog Block Array
Analog Ref.
Analog Input Muxing
Digital Clocks
Multiply Accum.
POR and LVD Decimator I 2C System Resets
Internal Voltage Ref.
Switch Mode Pump
SYSTEM RESOURCES
Cypress Semiconductor Corporation Document Number: 38-12012 Rev. *M
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised April 17, 2009
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PSoC Functional Overview
The PSoC(R) family consists of many Programmable System-on-Chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one, low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, as well as programmable interconnects. This architecture allows the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts and packages. The PSoC architecture, as illustrated on the left, is comprised of four main areas: PSoC Core, Digital System, Analog System, and System Resources. Configurable global busing allows all the device resources to be combined into a complete custom system. The PSoC CY8C27x43 family can have up to five IO ports that connect to the global digital and analog interconnects, providing access to 8 digital blocks and 12 analog blocks.
Digital System
The Digital System is composed of 8 digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Figure 1. Digital System Block Diagram
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
Digital Clocks FromCore
To System Bus
ToAnalog System
DIGITAL SYSTEM
Digital PSoC Block Array
Row Input Configuration
Row 0
DBB00 DBB01 DCB02
4 DCB03 4
Row Output Configuration
PSoC Core
The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose IO). The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU utilizes an interrupt controller with 17 vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers (WDT). Memory encompasses 16K of Flash for program storage, 256 bytes of SRAM for data storage, and up to 2K of EEPROM emulated using the Flash. Program Flash utilizes four protection levels on blocks of 64 bytes, allowing customized software IP protection. The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate to 2.5% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz ILO (internal low speed oscillator) is provided for the Sleep timer and WDT. If crystal accuracy is desired, the ECO (32.768 kHz external crystal oscillator) is available for use as a Real Time Clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device. PSoC GPIOs provide connection to the CPU, digital and analog resources of the device. Each pin's drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read.
8 8
8
Row Input Configuration
Row 1
DBB10 DBB11 DCB12
4 DCB13 4
8 Row Output Configuration
GIE[7:0] GIO[7:0]
Global Digital Interconnect
GOE[7:0] GOO[7:0]
Digital peripheral configurations include those listed below.

PWMs (8 to 32 bit) PWMs with Dead band (8 to 32 bit) Counters (8 to 32 bit) Timers (8 to 32 bit) UART 8 bit with selectable parity (up to 2) SPI slave and master (up to 2) I2C slave and multi-master (1 available as a System Resource) Cyclical Redundancy Checker/Generator (8 to 32 bit) IrDA (up to 2) Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows you the optimum choice of system resources for your application. Family resources are shown in the table titled "PSoC Device Characteristics" on page 4.
Document Number: 38-12012 Rev. *M
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Analog System
The Analog System is composed of 12 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common PSoC analog functions (most available as user modules) are listed below.

Figure 2. Analog System Block Diagram
P0[7] P0[5] P0[3] P0[1] AGNDIn RefIn P0[6] P0[4] P0[2] P0[0] P2[6]
Analog-to-digital converters (up to 4, with 6- to 14-bit resolution, selectable as Incremental, Delta Sigma, and SAR) Filters (2, 4, 6, and 8 pole band-pass, low-pass, and notch) Amplifiers (up to 4, with selectable gain to 48x) Instrumentation amplifiers (up to 2, with selectable gain to 93x) Comparators (up to 4, with 16 selectable thresholds) DACs (up to 4, with 6- to 9-bit resolution) Multiplying DACs (up to 4, with 6- to 9-bit resolution) High current output drivers (four with 30 mA drive as a Core Resource) 1.3V reference (as a System Resource) DTMF Dialer Modulators Correlators Peak detectors Many other topologies possible
P2[3]
P2[4] P2[2] P2[0]
P2[1]
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
ACI2[1:0]
ACI3[1:0]
Block Array
ACB00 ASC10 ASD20 ACB01 ASD11 ASC21 ACB02 ASC12 ASD22 ACB03 ASD13 ASC23
Analog blocks are provided in columns of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks, as shown in the figure below.
Interface to Digital System RefHi RefLo AGND
Analog Reference
Reference Generators AGNDIn RefIn Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
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Additional System Resources
System Resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, switch mode pump, low voltage detection, and power on reset. Statements describing the merits of each system resource are below.
Getting Started
The quickest way to understand PSoC silicon is to read this data sheet and then use the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in depth information, along with detailed programming information, see the PSoC(R) Programmable System-on-ChipTM Technical Reference Manual for CY8C28xxx PSoC devices. For up to date ordering, packaging, and electrical specification information, see the latest PSoC device data sheets on the web at www.cypress.com/psoc.
Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. Multiply accumulate (MAC) provides fast 8-bit multiplier with 32-bit accumulate, to assist in general math and digital filters. The decimator provides a custom hardware filter for digital signal processing applications including the creation of Delta Sigma ADCs. The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.3V reference provides an absolute reference for the analog system, including ADCs and DACs. An integrated switch mode pump (SMP) generates normal operating voltages from a single 1.2V battery cell, providing a low cost boost converter.

Application Notes
Application notes are an excellent introduction to the wide variety of possible PSoC designs. They are located here: www.cypress.com/psoc. Select Application Notes under the Documentation tab.
Development Kits
PSoC Development Kits are available online from Cypress at www.cypress.com/shop and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark.

Training
Free PSoC technical training (on demand, webinars, and workshops) is available online at www.cypress.com/training. The training covers a wide variety of topics and skill levels to assist you in your designs.
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. The following table lists the resources available for specific PSoC device groups.The PSoC device covered by this data sheet is highlighted below. Table 1. PSoC Device Characteristics
Analog Columns Analog Outputs Analog Inputs Analog Blocks Digital Blocks Digital IO Digital Rows SRAM Size PSoC Part Number CY8C29x66 CY8C27x43 CY8C24x94 CY8C24x23 CY8C24x23A CY8C21x34 CY8C21x23 CY8C20x34 Flash Size
CYPros Consultants
Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to www.cypress.com/cypros.
Solutions Library
Visit our growing library of solution focused designs at www.cypress.com/solutions. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly.
up to 64 up to 44 49 up to 24 up to 24 up to 28 16 up to 28
4 2 1 1 1 1 1 0
16 8 4 4 4 4 4 0
12 12 48 12 12 28 8 28
4 4 2 2 2 0 0 0
4 4 2 2 2 2 2 0
12 12 6 6 6 4[1] 4[2] 3[2]
2K 256 Bytes 1K 256 Bytes 256 Bytes 512 Bytes 256 Bytes 512 Bytes
32K 16K 16K 4K 4K 8K 4K 8K
Technical Support
For assistance with technical issues, search KnowledgeBase articles and forums at www.cypress.com/support. If you cannot find an answer to your question, call technical support at 1-800-541-4736.
Notes 1. Limited analog functionality. 2. Two analog blocks and one CapSense.
Document Number: 38-12012 Rev. *M
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Development Tools
PSoC Designer is a Microsoft(R) Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE runs on Windows XP or Windows Vista. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and built in support for third party assemblers and C compilers. PSoC Designer also supports C language compilers developed specifically for the devices in the PSoC family.
Code Generation Tools PSoC Designer supports multiple third party C compilers and assemblers. The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. The choice is yours. Assemblers. The assemblers allow assembly code to merge seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all the features of C tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started.
PSoC Designer Software Subsystems
System-Level View A drag-and-drop visual embedded system design environment based on PSoC Express. In the system level view you create a model of your system inputs, outputs, and communication interfaces. You define when and how an output device changes state based upon any or all other system devices. Based upon the design, PSoC Designer automatically selects one or more PSoC Programmable System-on-Chip Controllers that match your system requirements. PSoC Designer generates all embedded code, then compiles and links it into a programming file for a specific PSoC device. Chip-Level View The chip-level view is a more traditional integrated development environment (IDE) based on PSoC Designer 4.4. Choose a base device to work with and then select different onboard analog and digital components called user modules that use the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time. Hybrid Designs You can begin in the system-level view, allow it to choose and configure your user modules, routing, and generate code, then switch to the chip-level view to gain complete control over on-chip resources. All views of the project share a common code editor, builder, and common debug, emulation, and programming tools.
In-Circuit Emulator
A low cost, high functionality In-Circuit Emulator (ICE) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation.
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Designing with PSoC Designer
The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user selectable functions. The PSoC development process can be summarized in the following four steps: 1. Select Components 2. Configure Components 3. Organize and Connect 4. Generate, Verify, and Debug
Organize and Connect
You can build signal chains at the chip level by interconnecting user modules to each other and the IO pins, or connect system level inputs, outputs, and communication interfaces to each other with valuator functions. In the system-level view, selecting a potentiometer driver to control a variable speed fan driver and setting up the valuators to control the fan speed based on input from the pot selects, places, routes, and configures a programmable gain amplifier (PGA) to buffer the input from the potentiometer, an analog to digital converter (ADC) to convert the potentiometer's output to a digital signal, and a PWM to control the fan. In the chip-level view, perform the selection, configuration, and routing so that you have complete control over the use of all on-chip resources.
Select Components
Both the system-level and chip-level views provide a library of prebuilt, pretested hardware peripheral components. In the system-level view, these components are called "drivers" and correspond to inputs (a thermistor, for example), outputs (a brushless DC fan, for example), communication interfaces (I2C-bus, for example), and the logic to control how they interact with one another (called valuators). In the chip-level view, the components are called "user modules". User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and programmable system-on-chip varieties.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move on to developing code for the project, perform the "Generate Application" step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. Both system-level and chip-level designs generate software based on your design. The chip-level design provides application programming interfaces (APIs) with high level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. The system-level design also generates a C main() program that completely controls the chosen application and contains placeholders for custom code at strategic positions allowing you to further refine the software without disrupting the generated code. A complete code development environment allows you to develop and customize your applications in C, assembly language, or both. The last step in the development process takes place inside PSoC Designer's Debugger subsystem. The Debugger downloads the HEX image to the ICE where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals.
Configure Components
Each of the components you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a Pulse Width Modulator (PWM) User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. Both the system-level drivers and chip-level user modules are documented in data sheets that are viewed directly in PSoC Designer. These data sheets explain the internal operation of the component and provide performance specifications. Each data sheet describes the use of each user module parameter or driver property, and other information you may need to successfully implement your design.
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Document Conventions
Acronyms Used
This table lists the acronyms used in this data sheet. Table 2. Acronyms Acronym AC ADC API CPU CT DAC DC EEPROM FSR GPIO ICE IDE IO ISSP IPOR LSb LVD MSb PC PGA POR PPOR PSoC(R) PWM ROM SC SMP SRAM Description alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current electrically erasable programmable read-only memory full scale range general purpose IO in-circuit emulator integrated development environment input/output in-system serial programming imprecise power on reset least-significant bit low voltage detect most-significant bit program counter programmable gain amplifier power on reset precision power on reset Programmable System-on-ChipTM pulse width modulator read only memory switched capacitor switch mode pump static random access memory
Units of Measure
A units of measure table is located in the section Electrical Specifications on page 19. Table 13 on page 19 lists all the abbreviations used to measure the PSoC devices.
Numeric Naming
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexadecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (for example, 01010100b' or `01000011b'). Numbers not indicated by an `h', `b', or 0x are decimal.
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Pinouts
The CY8C27x43 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a "P") is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.
8-Pin Part Pinout
Table 3. Pin Definitions - 8-Pin PDIP
Pin No.
1 2 3 4 5 6 7 8 IO IO IO Power IO IO
Type Digital
IO IO IO Power
Analog
IO IO
Pin Name
P0[5] P0[3] P1[1] Vss P1[0] P0[2] P0[4] Vdd
Description
Analog column mux input and column output. Analog column mux input and column output. Crystal Input (XTALin), I2C Serial Clock (SCL), ISSP-SCLK*. Ground connection. Crystal Output (XTALout), I2C Serial Data (SDA), ISSP-SDATA*. Analog column mux input and column output. Analog column mux input and column output. Supply voltage.
Figure 3. CY8C27143 8-Pin PSoC Device
A, IO, P0[5] A, IO, P0[3] I2CSCL,XTALin, P1[1] Vss
1 8 2PDIP 7 3 6 4 5
Vdd P0[4], A, IO P0[2], A, IO P1[0],XTALout,I2CSDA
LEGEND: A = Analog, I = Input, and O = Output. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
20-Pin Part Pinout
Table 4. Pin Definitions - 20-Pin SSOP, SOIC
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 IO IO IO IO Power IO IO IO IO Input I IO IO I IO IO IO IO Power
Type Digital
IO IO IO IO Power
Analog
I IO IO I
Pin Name
P0[7] P0[5] P0[3] P0[1] SMP P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES P0[0] P0[2] P0[4] P0[6] Vdd
Description
Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Switch Mode Pump (SMP) connection to external components required. I2C Serial Clock (SCL). I2C Serial Data (SDA). Crystal Input (XTALin), I2C Serial Clock (SCL), ISSP-SCLK*. Ground connection. Crystal Output (XTALout), I2C Serial Data (SDA), ISSP-SDATA*. Optional External Clock Input (EXTCLK). Active high external reset with internal pull down. Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage.
Figure 4. CY8C27243 20-Pin PSoC Device
A, I, P0[7] A, IO, P0[5] A, IO, P0[3] A, I, P0[1] SMP I2CSCL,P1[7] I2CSDA, P1[5] P1[3] I2CSCL,XTALin, P1[1] Vss
1 2 3 4 5 6 7 8 9 10
SSOP SOIC
20 19 18 17 16 15 14 13 12 11
Vdd P0[6], A, I P0[4], A, IO P0[2], A, IO P0[0], A, I XRES P1[6] P1[4],EXTCLK P1[2] P1[0],XTALout,I2CSDA
LEGEND: A = Analog, I = Input, and O = Output. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
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28-Pin Part Pinout
Table 5. Pin Definitions - 28-Pin PDIP, SSOP, SOIC
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 IO IO IO IO IO IO IO IO Power I IO IO I IO IO IO IO Input I I IO IO IO IO Power Type
Digital
IO IO IO IO IO IO IO IO
Analog
I IO IO I
Pin Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5]
Description Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input.
Figure 5. CY8C27443 28-Pin PSoC Device
A, I, P0[7] A, IO, P0[5] A, IO, P0[3] A, I, P0[1] P2[7] P2[5] A, I, P2[3] A, I, P2[1] SMP I2CSCL,P1[7] I2CSDA, P1[5] P1[3] I2CSCL,XTALin, P1[1] Vss
I I Power
P2[3] P2[1] SMP P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd
Direct switched capacitor block input. Direct switched capacitor block input. Switch Mode Pump (SMP) connection to external components required. I2C Serial Clock (SCL). I2C Serial Data (SDA). Crystal Input (XTALin), I2C Serial Clock (SCL), ISSP-SCLK*. Ground connection. Crystal Output (XTALout), I2C Serial Data (SDA), ISSP-SDATA*. Optional External Clock Input (EXTCLK). Active high external reset with internal pull down. Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VRef). Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage.
1 2 3 4 5 6 7 8 9 10 11 12 13 14
PDIP SSOP SOIC
28 27 26 25 24 23 22 21 20 19 18 17 16 15
Vdd P0[6], A, I P0[4], A, IO P0[2], A, IO P0[0], A, I P2[6],ExternalVRef P2[4],ExternalAGND P2[2], A, I P2[0], A, I XRES P1[6] P1[4],EXTCLK P1[2] P1[0],XTALout,I2CSDA
LEGEND: A = Analog, I = Input, and O = Output. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
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44-Pin Part Pinout
Table 6. Pin Definitions - 44-Pin TQFP
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Type
Digital
IO IO IO IO IO IO IO
Analog
I I
Pin Name P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] P1[3] P1[1]
Description Direct switched capacitor block input. Direct switched capacitor block input.
Figure 6. CY8C27543 44-Pin PSoC Device
P0[6], A, I P0[4], A, IO P0[2], A, IO P0[0], A, I P2[6],ExternalVRef 33 32 31 30 29 28 27 26 25 24 23 P2[4], External AGND P2[2], A, I P2[0], A, I P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2]
Power IO IO IO IO IO IO IO IO Power IO IO IO IO IO IO IO IO Input IO IO IO IO IO IO IO IO IO IO IO IO Power IO IO IO IO IO I IO IO I
Switch Mode Pump (SMP) connection to external components required.
Vss P1[0] P1[2] P1[4] P1[6] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd P0[7] P0[5] P0[3] P0[1] P2[7]
Crystal Input (XTALin), I2C Serial Clock (SCL), ISSP-SCLK*. Ground connection. Crystal Output (XTALout), I2C Serial Data (SDA), ISSP-SDATA*. Optional External Clock Input (EXTCLK).
Active high external reset with internal pull down.
I I
I IO IO I
Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VRef). Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage. Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input.
LEGEND: A = Analog, I = Input, and O = Output. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 38-12012 Rev. *M
P3[1] I2CSCL, P1[7] I2C SDA, P1[5] P1[3] I2CSCL,XTALin,P1[1] Vss I2CSDA,XTALout,P1[0] P1[2] EXTCLK,P1[4] P1[6] P3[0]
I2C Serial Clock (SCL). I2C Serial Data (SDA).
12 13 14 15 16 17 18 19 20 21 22
P2[5] A, I, P2[3] A, I, P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3]
1 2 3 4 5 6 7 8 9 10 11
44 43 42 41 40 39 38 37 36 35 34
P2[7] P0[1], A, I P0[3], A, IO P0[5], A, IO P0[7], A, I Vdd
TQFP
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48-Pin Part Pinout
Table 7. 48-Pin Part Pinout (SSOP)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 IO IO IO IO IO IO IO I I IO IO IO IO IO IO IO IO IO IO Input IO IO IO IO IO IO IO IO IO IO Power Type Digital IO IO IO IO IO IO IO IO IO IO IO IO Power I I Analog I IO IO I Pin Name
P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4]
Figure 7. CY8C27643 48-Pin PSoC Device
Description Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input.
A, I, P0[7] A, IO, P0[5] A, IO, P0[3] A, I, P0[1] P2[7] P2[5] A, I, P2[3] A, I, P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] I2CSCL, P1[7] I2CSDA, P1[5] P1[3] I2CSCL,XTALin,P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Direct switched capacitor block input. Direct switched capacitor block input.
SSOP
Switch Mode Pump (SMP) connection to external components required.
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
Vdd P0[6], A, I P0[4], A, IO P0[2], A, IO P0[0], A, I P2[6],External VRef P2[4],External AGND P2[2], A, I P2[0], A, I P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0] P5[2] P5[0] P1[6] P1[4],EXTCLK P1[2] P1[0],XTALout,I2C SDA
I2C Serial Clock (SCL). I2C Serial Data (SDA). Crystal Input (XTALin), I2C Serial Clock (SCL), ISSP-SCLK*. Ground connection. Crystal Output (XTALout), I2C Serial Data (SDA), ISSP-SDATA.* Optional External Clock Input (EXTCLK).
Active high external reset with internal pull down.
Direct switched capacitor block input. Direct switched capacitor block input.
External Analog Ground (AGND).
Document Number: 38-12012 Rev. *M
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Table 7. 48-Pin Part Pinout (SSOP)
43 44 45 46 47 48 IO IO IO IO IO I IO IO I
P2[6] P0[0] P0[2] P0[4] P0[6] Vdd
Power
External Voltage Reference (VRef). Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
Table 8. 48-Pin Part Pinout (QFN)*
Pi Type n No Digital Analog . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 IO IO IO IO IO IO IO IO IO IO IO IO IO IO Input IO IO IO IO IO IO IO IO IO IO Power IO IO IO IO IO IO Power I I Pin Name P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] Active high external reset with internal pull down. Optional External Clock Input (EXTCLK). Crystal Input (XTALin), I2C Serial Clock (SCL), ISSP-SCLK**. Ground connection. Crystal Output (XTALout), I2C Serial Data (SDA), ISSP-SDATA**. I2C Serial Clock (SCL). I2C Serial Data (SDA). Switch Mode Pump (SMP) connection to external components required.
A, I, P2[3] A, I, P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3]
Figure 8. CY8C27643 48-Pin PSoC Device
Description Direct switched capacitor block input.
P2[5] P2[7] P0[1], A,I P0[3], A,IO P0[5], A,IO P0[7], A,I Vdd P0[6], A,I P0[4], A,IO P0[2], A,IO P0[0], A,I P2[6],ExternalVRef 36 35 34 33 32 31 30 29 28 27 26 25 P2[4],External AGND P2[2], A, I P2[0], A, I P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0]
Direct switched capacitor block input.
Document Number: 38-12012 Rev. *M
13 14 I2CSDA,P1[5] 15 P1[3] 16 I2CSCL,XTALin,P1[1] 17 Vss 18 I2CSDA,XTALout,P1[0] 19 P1[2] 20 EXTCLK,P1[4] 21 P1[6] 22 P5[0] 23 P5[2] 24
1 2 3 4 5 6 7 8 9 10 11 12
P5[1] I2CSCL,P1[7]
48 47 46 45 44 43 42 41 40 39 38 37
QFN
(Top View )
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Table 8. 48-Pin Part Pinout (QFN)*
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 IO IO IO IO IO IO IO IO IO IO IO IO IO IO Power I IO IO I I IO IO I I I P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VRef). Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage. Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input.
LEGEND: A = Analog, I = Input, and O = Output. * The QFN package has a center pad that must be connected to ground (Vss). ** These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
Document Number: 38-12012 Rev. *M
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56-Pin Part Pinout
The 56-pin SSOP part is for the CY8C27002 On-Chip Debug (OCD) PSoC device. Note This part is only used for in-circuit debugging. It is NOT available for production. Table 9. 56-Pin Part Pinout (SSOP)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 IO IO IO IO IO IO IO IO IO IO IO IO Power IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO OCD OCD Power I I I I I I I I Type Digital Analog Pin Name NC P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] OCDE OCD even data IO. OCDO OCD odd data output. SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] NC P1[3] P1[1] Vdd NC NC P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] Optional External Clock Input (EXTCLK). Crystal Input (XTALin), I2C Serial Clock (SCL), ISSP-SCLK*. Supply voltage. No connection. No connection.. Crystal Output (XTALout), I2C Serial Data (SDA), ISSP-SDATA*. I2C Serial Clock (SCL). I2C Serial Data (SDA). No connection. Switch Mode Pump (SMP) connection to required external components. Direct switched capacitor block input. Direct switched capacitor block input.
Figure 9. CY8C27002 56-Pin PSoC Device
Description No connection. Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input.
NC AI, P0[7] AIO, P0[5] AIO, P0[3] AI, P0[1] P2[7] P2[5] AI, P2[3] AI, P2[1] P4[7] P4[5] P4[3] P4[1] OCDE OCDO SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] I2C SCL, P1[7] I2C SDA, P1[5] NC P1[3] SCLK, I2C SCL, XTALIn, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 Vdd P0[6], AI P0[4], AIO P0[2], AIO P0[0], AI P2[6], External VRef P2[4], External AGND P2[2], AI P2[0], AI P4[6] P4[4] P4[2] P4[0] CCLK HCLK XRES P3[6] P3[4] P3[2] P3[0] P5[2] P5[0] P1[6] P1[4], EXTCLK P1[2] P1[0], XTALOut, I2C SDA, SDATA NC NC
SSOP
Not for Production
Document Number: 38-12012 Rev. *M
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Table 9. 56-Pin Part Pinout (SSOP)
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Input OCD OCD IO IO IO IO IO IO IO IO IO IO IO IO Power I I I I I I XRES HCLK CCLK P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VRef). Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage. Active high external reset with internal pull down. OCD high-speed clock output. OCD CPU clock output.
LEGEND: A = Analog, I = Input, O = Output, and OCD = On-Chip Debug. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
Document Number: 38-12012 Rev. *M
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Register Reference
This chapter lists the registers of the CY8C27x43 PSoC device. For detailed register information, reference the PSoC Programmable System-on-Chip Technical Reference Manual.
Register Mapping Tables
The PSoC device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1. Note In the following register mapping tables, blank fields are reserved and must not be accessed.
Register Conventions
The register conventions specific to this section are listed in the following table. Table 10. Register Conventions Convention R W L C # Description Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific
Table 11. Register Map Bank 0 Table: User Space
Access Access Access Access Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Name Name Name
00 RW 01 RW 02 RW 03 RW 04 RW 05 RW 06 RW 07 RW 08 RW 09 RW 0A RW 0B RW 0C RW 0D RW 0E RW 0F RW 10 RW 11 RW 12 RW 13 RW 14 RW 15 RW 16 RW 17 RW 18 19 1A 1B 1C 1D 1E 1F DBB00DR0 20 # AMX_IN DBB00DR1 21 W DBB00DR2 22 RW DBB00CR0 23 # ARF_CR DBB01DR0 24 # CMP_CR0 DBB01DR1 25 W ASY_CR Blank fields are Reserved and must not be accessed.
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65
ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 RW
RW # #
80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 # Access is bit specific.
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR3 INT_MSK3 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5
RW # RW # RW RW RW RW RW RW RC W RC RC
Document Number: 38-12012 Rev. *M
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Table 11. Register Map Bank 0 Table: User Space (continued)
Access Access Access Access Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Name Name Name Name
DBB01DR2 26 RW CMP_CR1 DBB01CR0 27 # DCB02DR0 28 # DCB02DR1 29 W DCB02DR2 2A RW DCB02CR0 2B # DCB03DR0 2C # DCB03DR1 2D W DCB03DR2 2E RW DCB03CR0 2F # DBB10DR0 30 # ACB00CR3 DBB10DR1 31 W ACB00CR0 DBB10DR2 32 RW ACB00CR1 DBB10CR0 33 # ACB00CR2 DBB11DR0 34 # ACB01CR3 DBB11DR1 35 W ACB01CR0 DBB11DR2 36 RW ACB01CR1 DBB11CR0 37 # ACB01CR2 DCB12DR0 38 # ACB02CR3 DCB12DR1 39 W ACB02CR0 DCB12DR2 3A RW ACB02CR1 DCB12CR0 3B # ACB02CR2 DCB13DR0 3C # ACB03CR3 DCB13DR1 3D W ACB03CR0 DCB13DR2 3E RW ACB03CR1 DCB13CR0 3F # ACB03CR2 Blank fields are Reserved and must not be accessed.
66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F
RW
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 RDI1RI B8 RDI1SYN B9 RDI1IS BA RDI1LT0 BB RDI1LT1 BC RDI1RO0 BD RDI1RO1 BE BF # Access is bit specific.
DEC_CR0 DEC_CR1 MUL_X MUL_Y MUL_DH MUL_DL ACC_DR1 ACC_DR0 ACC_DR3 ACC_DR2 RW RW RW RW RW RW RW CPU_F RW RW RW RW RW RW RW
CPU_SCR1 CPU_SCR0
E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF
RW RW W W R R RW RW RW RW
RL
# #
Table 12. Register Map Bank 1 Table: Configuration Space
Access Access Access Access Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Name Name Name
00 RW 01 RW 02 RW 03 RW 04 RW 05 RW 06 RW 07 RW 08 RW 09 RW 0A RW 0B RW 0C RW 0D RW 0E RW 0F RW 10 RW 11 RW 12 RW 13 RW 14 RW 15 RW 16 RW 17 RW 18 19 1A 1B Blank fields are Reserved and must not be accessed.
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B
ASC10CR0 80 ASC10CR1 81 ASC10CR2 82 ASC10CR3 83 ASD11CR0 84 ASD11CR1 85 ASD11CR2 86 ASD11CR3 87 ASC12CR0 88 ASC12CR1 89 ASC12CR2 8A ASC12CR3 8B ASD13CR0 8C ASD13CR1 8D ASD13CR2 8E ASD13CR3 8F ASD20CR0 90 ASD20CR1 91 ASD20CR2 92 ASD20CR3 93 ASC21CR0 94 ASC21CR1 95 ASC21CR2 96 ASC21CR3 97 ASD22CR0 98 ASD22CR1 99 ASD22CR2 9A ASD22CR3 9B # Access is bit specific.
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB
RW RW RW RW
Document Number: 38-12012 Rev. *M
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Table 12. Register Map Bank 1 Table: Configuration Space (continued)
Access Access Access Access Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Name Name Name Name
1C 1D 1E 1F DBB00FN 20 RW CLK_CR0 DBB00IN 21 RW CLK_CR1 DBB00OU 22 RW ABF_CR0 23 AMD_CR0 DBB01FN 24 RW DBB01IN 25 RW DBB01OU 26 RW AMD_CR1 27 ALT_CR0 DCB02FN 28 RW ALT_CR1 DCB02IN 29 RW CLK_CR2 DCB02OU 2A RW 2B DCB03FN 2C RW DCB03IN 2D RW DCB03OU 2E RW 2F DBB10FN 30 RW ACB00CR3 DBB10IN 31 RW ACB00CR0 DBB10OU 32 RW ACB00CR1 33 ACB00CR2 DBB11FN 34 RW ACB01CR3 DBB11IN 35 RW ACB01CR0 DBB11OU 36 RW ACB01CR1 37 ACB01CR2 DCB12FN 38 RW ACB02CR3 DCB12IN 39 RW ACB02CR0 DCB12OU 3A RW ACB02CR1 3B ACB02CR2 DCB13FN 3C RW ACB03CR3 DCB13IN 3D RW ACB03CR0 DCB13OU 3E RW ACB03CR1 3F ACB03CR2 Blank fields are Reserved and must not be accessed.
5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F
RW RW RW RW
RW RW RW RW
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 RDI1RI B8 RDI1SYN B9 RDI1IS BA RDI1LT0 BB RDI1LT1 BC RDI1RO0 BD RDI1RO1 BE BF # Access is bit specific.
ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3
RW RW RW RW
OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP
IMO_TR ILO_TR BDG_TR ECO_TR
RW RW RW RW RW RW RW CPU_F RW RW RW RW RW RW RW
CPU_SCR1 CPU_SCR0
DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF
RW RW RW RW RW RW RW R
W W RW W
RL
# #
Document Number: 38-12012 Rev. *M
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Electrical Specifications
This chapter presents the DC and AC electrical specifications of the CY8C27x43 PSoC device. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc. Specifications are valid for -40C TA 85C and TJ 100C, except where noted. Specifications for devices running at greater than 12 MHz are valid for -40C TA 70C and TJ 82C. Figure 10. Voltage versus CPU Frequency
5.25
4.75 Vdd Voltage 3.00 93 kHz
CPU Fre que ncy
The following table lists the units of measure that are used in this chapter. Table 13. Units of Measure Symbol
oC
O
l id g Va atin n r pe gio Re
12 MHz 24 MHz
Unit of Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square
Symbol W mA ms mV nA ns nV W pA pF pp ppm ps sps s V
Unit of Measure microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts
dB fF Hz KB Kbit kHz k MHz M A F H s V Vrms
Document Number: 38-12012 Rev. *M
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Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 14. Absolute Maximum Ratings Symbol TSTG Description Storage Temperature Min -55 Typ 25 Max +100 Unit
oC
Notes Higher storage temperatures reduce data retention time. Recommended storage temperature is +25C 25C. Extended duration storage temperatures above 65oC degrade reliability.
TA Vdd VIO VIOZ IMIO IMAIO ESD LU
Ambient Temperature with Power Applied Supply Voltage on Vdd Relative to Vss DC Input Voltage DC Voltage Applied to Tri-state Maximum Current into any Port Pin Maximum Current into any Port Pin Configured as Analog Driver Electro Static Discharge Voltage Latch up Current
-40 -0.5 Vss- 0.5 Vss 0.5 -25 -50 2000 -
- - - - - - - -
+85 +6.0 Vdd + 0.5 Vdd + 0.5 +50 +50 - 200
oC
V V V mA mA V mA Human Body Model ESD.
Operating Temperature
Table 15. Operating Temperature Symbol Description TA Ambient Temperature TJ Junction Temperature Min -40 -40 Typ - - Max +85 +100 Unit oC oC Notes The temperature rise from ambient to junction is package specific. See "Thermal Impedances" on page 46. The user must limit the power consumption to comply with this requirement.
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DC Electrical Characteristics
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 16. DC Chip-Level Specifications Symbol Description Vdd Supply Voltage IDD Supply Current Min 3.00 - Typ - 5 Max 5.25 8 Unit V mA Notes Conditions are Vdd = 5.0V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz. Conditions are Vdd = 3.3V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz. Conditions are with internal slow speed oscillator, Vdd = 3.3V, -40 oC TA 55 oC. Conditions are with internal slow speed oscillator, Vdd = 3.3V, 55 oC < TA 85 oC. Conditions are with properly loaded, 1 W max, 32.768 kHz crystal. Vdd = 3.3V, -40 oC TA 55 oC. Conditions are with properly loaded, 1 W max, 32.768 kHz crystal. Vdd = 3.3V, 55 oC < TA 85 oC. Trimmed for appropriate Vdd. Trimmed for appropriate Vdd.
IDD3
Supply Current
-
3.3
6.0
mA
ISB ISBH ISBXTL
Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT.[3] Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT at high temperature.[3] Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal.[3]
-
3
6.5
A A A A
-
4
25
-
4
7.5
ISBXTLH Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal at high temperature.[3] VREF Reference Voltage (Bandgap) for Silicon A [4] VREF Reference Voltage (Bandgap) for Silicon B [4]
-
5
26
1.275 1.280
1.300 1.300
1.325 1.320
V V
Notes 3. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This must be compared with devices that have similar functions enabled. 4. Refer to the "Ordering Information" on page 50.
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DC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 17. DC GPIO Specifications Symbol Description Pull up Resistor RPU Pull down Resistor RPD VOH High Output Level Min 4 4 Vdd 1.0 Typ 5.6 5.6 - Max 8 8 - Unit k k V Notes
VOL
Low Output Level
-
-
0.75
V
VIL VIH VH IIL CIN COUT
Input Low Level Input High Level Input Hysterisis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output
- 2.1 - - - -
- - 60 1 3.5 3.5
0.8 - - 10 10
V V mV nA pF pF
IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). Vdd = 3.0 to 5.25 Vdd = 3.0 to 5.25 Gross tested to 1 A. Package and pin dependent. Temp = 25oC. Package and pin dependent. Temp = 25oC.
DC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at 25C and are for design guidance only. Table 18. 5V DC Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Min - - - - - - 0.0 0.5 Typ 1.6 1.3 1.2 7.0 20 4.5 - - Max 10 8 7.5 35.0 - 9.5 Vdd Vdd - 0.5 Unit mV mV mV V/oC pA Gross tested to 1 A. pF Package and pin dependent. Temp = 25oC. V The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. Notes
TCVOSOA Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) IEBOA Input Capacitance (Port 0 Analog Pins) CINOA VCMOA Common Mode Voltage Range Common Mode Voltage Range (high power or high opamp bias)
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Table 18. 5V DC Operational Amplifier Specifications (continued) Symbol CMRROA Description Common Mode Rejection Ratio Power = Low Power = Medium Power = High Open Loop Gain Power = Low Power = Medium Power = High Min 60 60 60 Typ - Max - Unit dB Notes Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB. Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB.
GOLOA
60 60 80
-
-
dB
VOHIGHOA High Output Voltage Swing (internal signals) Power = Low Power = Medium Power = High VOLOWOA Low Output Voltage Swing (internal signals) Power = Low Power = Medium Power = High ISOA Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High PSRROA Supply Voltage Rejection Ratio Table 19. 3.3V DC Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High High Power is 5 Volts Only Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range
Vdd - 0.2 Vdd - 0.2 Vdd - 0.5 - - - - - - - - - 60
- - - - - - 150 300 600 1200 2400 4600 -
- - - 0.2 0.2 0.5 200 400 800 1600 3200 6400 -
V V V V V V A A A A A A dB Vss VIN (Vdd - 2.25) or (Vdd - 1.25V) VIN Vdd.
Min - - - - - 0.2
Typ 1.65 1.32 7.0 20 4.5 -
Max 10 8 35.0 - 9.5 Vdd - 0.2
Unit mV mV V/oC pA pF V
Notes
TCVOSOA Average Input Offset Voltage Drift IEBOA CINOA VCMOA
Gross tested to 1 A. Package and pin dependent. Temp = 25oC. The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB.
CMRROA
Common Mode Rejection Ratio Power = Low Power = Medium Power = High
50 50 50
-
-
dB
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Table 19. 3.3V DC Operational Amplifier Specifications (continued) Symbol GOLOA Description Open Loop Gain Power = Low Power = Medium Power = High Min 60 60 80 Typ - Max - Unit dB Notes Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB.
VOHIGHOA High Output Voltage Swing (internal signals) Power = Low Power = Medium Power = High is 5V only VOLOWOA Low Output Voltage Swing (internal signals) Power = Low Power = Medium Power = High ISOA Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High Supply Voltage Rejection Ratio
Vdd - 0.2 Vdd - 0.2 Vdd - 0.2 - - - - - - - - - 50
- - - - - - 150 300 600 1200 2400 4600 80
- - - 0.2 0.2 0.2 200 400 800 1600 3200 6400 -
V V V V V V A A A A A A dB Vss VIN (Vdd - 2.25) or (Vdd - 1.25V) VIN Vdd.
PSRROA
DC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V at 25C and are for design guidance only. Table 20. DC Low Power Comparator Specifications Symbol VREFLPC ISLPC VOSLPC Description Low power comparator (LPC) reference voltage range LPC supply current LPC voltage offset Min 0.2 - - Typ - 10 2.5 Max Vdd - 1 40 30 Unit V A mV
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DC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 21. 5V DC Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB VOHIGHOB Description Min Input Offset Voltage (Absolute Value) - Average Input Offset Voltage Drift - Common-Mode Input Voltage Range 0.5 Output Resistance Power = Low - Power = High - High Output Voltage Swing (Load = 32 ohms to Vdd/2) 0.5 x Vdd + 1.3 Power = Low 0.5 x Vdd + 1.3 Power = High Low Output Voltage Swing (Load = 32 ohms - to Vdd/2) - Power = Low Power = High Supply Current Including Bias Cell (No Load) Power = Low - Power = High - Supply Voltage Rejection Ratio 60 Typ 3 +6 - 1 1 - - Max 12 - Vdd - 1.0 - - - - Unit mV V/C V W W V V
VOLOWOB
- -
0.5 x Vdd - 1.3 0.5 x Vdd - 1.3
V V
ISOB PSRROB
1.1 2.6 64
5.1 8.8 -
mA mA dB
Table 22. 3.3V DC Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB VOHIGHOB Description Min Input Offset Voltage (Absolute Value) - Average Input Offset Voltage Drift - Common-Mode Input Voltage Range 0.5 Output Resistance Power = Low - Power = High - High Output Voltage Swing (Load = 1k ohms to Vdd/2) 0.5 x Vdd + 1.0 Power = Low 0.5 x Vdd + 1.0 Power = High Low Output Voltage Swing (Load = 1k ohms to Vdd/2) - Power = Low - Power = High Supply Current Including Bias Cell (No Load) Power = Low - Power = High Supply Voltage Rejection Ratio 60 Typ 3 +6 1 1 - - Max 12 - Vdd - 1.0 - - - - Units mV V/C V W W V V
VOLOWOB
- -
0.5 x Vdd - 1.0 0.5 x Vdd - 1.0
V V
ISOB PSRROB
0.8 2.0 64
2.0 4.3 -
mA mA dB
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DC Switch Mode Pump Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 23. DC Switch Mode Pump (SMP) Specifications Symbol VPUMP 5V VPUMP 3V IPUMP VBAT5V VBAT3V VBATSTART VPUMP_Line Description 5V Output Voltage Min 4.75 Typ 5.0 Max 5.25 Unit V Notes Configuration of footnote.[5] Average, neglecting ripple. SMP trip voltage is set to 5.0V. Configuration of footnote.[5] Average, neglecting ripple. SMP trip voltage is set to 3.25V. Configuration of footnote.[5] SMP trip voltage is set to 3.25V. SMP trip voltage is set to 5.0V. Configuration of footnote.[5] SMP trip voltage is set to 5.0V. Configuration of footnote.[5] SMP trip voltage is set to 3.25V. Configuration of footnote.[5] Configuration of footnote.[5] VO is the "Vdd Value for PUMP Trip" specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 29 on page 30. Configuration of footnote.[5] VO is the "Vdd Value for PUMP Trip" specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 29 on page 30.
3V Output Voltage
3.00
3.25
3.60
V
Available Output Current VBAT = 1.5V, VPUMP = 3.25V VBAT = 1.8V, VPUMP = 5.0V Input Voltage Range from Battery Input Voltage Range from Battery Minimum Input Voltage from Battery to Start Pump Line Regulation (over VBAT range)
8 5 1.8 1.0 1.1 -
- - - - - 5
- - 5.0 3.3 - -
mA mA V V V %VO
VPUMP_Load
Load Regulation
-
5
-
%VO
VPUMP_Ripple Output Voltage Ripple (depends on capacitor/load) E3 FPUMP DCPUMP Efficiency Switching Frequency Switching Duty Cycle
- 35 - -
100 50 1.3 50
- - - -
mVpp Configuration of footnote.[5] Load is 5 mA. % MHz % Configuration of footnote.[5] Load is 5 mA. SMP trip voltage is set to 3.25V.
Note 5. L1 = 2 mH inductor, C1 = 10 mF capacitor, D1 = Schottky diode. See Figure 11.
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Figure 11. Basic Switch Mode Pump Circuit
D1
Vdd
V PUMP C1
L1 V BAT
+
SMP Battery
PSoC TM
Vss
DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high. Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some coupling of the digital signal may appear on the AGND. Table 24. Silicon Revision A - 5V DC Analog Reference Specifications Symbol BG - - - - - - - - - - - - - - - - - Description Bandgap Voltage Reference AGND = Vdd/2[6] AGND = 2 x BandGap[6] AGND = P2[4] (P2[4] = Vdd/2)[6] AGND = BandGap[6] AGND = 1.6 x BandGap[6] AGND Block to Block Variation (AGND = Vdd/2)[6] RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) RefHi = 3.2 x BandGap RefLo = Vdd/2 - BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) RefLo = P2[4] - BandGap (P2[4] = Vdd/2) RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) Min 1.274 Vdd/2 - 0.030 2 x BG - 0.043 P2[4] - 0.013 BG - 0.009 1.6 x BG - 0.018 -0.034 Vdd/2 + BG - 0.140 3 x BG - 0.112 2 x BG + P2[6] - 0.113 P2[4] + BG - 0.130 P2[4] + P2[6] - 0.133 3.2 x BG - 0.112 Vdd/2 - BG - 0.051 BG - 0.082 2 x BG - P2[6] - 0.084 P2[4] - BG - 0.056 P2[4] - P2[6] - 0.057 Typ 1.30 Vdd/2 - 0.004 2 x BG - 0.010 P2[4] BG 1.6 x BG 0.000 Vdd/2 + BG - 0.018 3 x BG - 0.018 2 x BG + P2[6] - 0.018 P2[4] + BG - 0.016 P2[4] + P2[6] - 0.016 3.2 x BG Vdd/2 - BG + 0.024 BG + 0.023 2 x BG - P2[6] + 0.025 P2[4] - BG + 0.026 P2[4] - P2[6] + 0.026 Max 1.326 Vdd/2 + 0.003 2 x BG + 0.024 P2[4] + 0.014 BG + 0.009 1.6 x BG + 0.018 0.034 Vdd/2 + BG + 0.103 3 x BG + 0.076 2 x BG + P2[6] + 0.077 P2[4] + BG + 0.098 P2[4] + P2[6] + 0.100 3.2 x BG + 0.076 Vdd/2 - BG + 0.098 BG + 0.129 2 x BG - P2[6] + 0.134 P2[4] - BG + 0.107 P2[4] - P2[6] + 0.110 Unit V V V V V V V V V V V V V V V V V V
Note 6. AGND tolerance includes the offsets of the local buffer in the PSoC block.
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Table 25. Silicon Revision B - 5V DC Analog Reference Specifications Symbol BG - - - - - - - - - - - - - - - - - Description Bandgap Voltage Reference AGND = Vdd/2[7] AGND = 2 x BandGap[7] AGND = P2[4] (P2[4] = Vdd/2)[7] AGND = BandGap[7] AGND = 1.6 x BandGap[7] AGND Block to Block Variation (AGND = Vdd/2)[7] RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) RefHi = 3.2 x BandGap RefLo = Vdd/2 - BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) RefLo = P2[4] - BandGap (P2[4] = Vdd/2) RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) Min 1.28 Vdd/2 - 0.030 2 x BG - 0.043 P2[4] - 0.011 BG - 0.009 1.6 x BG - 0.018 -0.034 Vdd/2 + BG - 0.1 3 x BG - 0.06 2 x BG + P2[6] - 0.06 P2[4] + BG - 0.06 P2[4] + P2[6] - 0.06 3.2 x BG - 0.06 Vdd/2 - BG - 0.051 BG - 0.06 2 x BG - P2[6] - 0.04 P2[4] - BG - 0.056 P2[4] - P2[6] - 0.056 1.30 Vdd/2 2 x BG P2[4] BG 1.6 x BG 0.000 Vdd/2 + BG - 0.01 3 x BG - 0.01 2 x BG + P2[6] - 0.01 P2[4] + BG - 0.01 P2[4] + P2[6] - 0.01 3.2 x BG - 0.01 Vdd/2 - BG + 0.01 BG + 0.01 2 x BG - P2[6] + 0.01 P2[4] - BG + 0.01 P2[4] - P2[6] + 0.01 Typ Max 1.32 Vdd/2 + 0.007 2 x BG + 0.024 P2[4] + 0.011 BG + 0.009 1.6 x BG + 0.018 0.034 Vdd/2 + BG + 0.1 3 x BG + 0.06 2 x BG + P2[6] + 0.06 P2[4] + BG + 0.06 P2[4] + P2[6] + 0.06 3.2 x BG + 0.06 Vdd/2 - BG + 0.06 BG + 0.06 2 x BG - P2[6] + 0.04 P2[4] - BG + 0.056 P2[4] - P2[6] + 0.056 Unit V V V V V V V V V V V V V V V V V V
Table 26. Silicon Revision A - 3.3V DC Analog Reference Specifications Symbol BG - - - - - - - - - - - - - Description Bandgap Voltage Reference AGND = Vdd/2[8] AGND = 2 x BandGap[8] AGND = P2[4] (P2[4] = Vdd/2) AGND = BandGap[8] AGND = 1.6 x BandGap[8] AGND Block to Block Variation (AGND = Vdd/2)[8] RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) RefHi = 3.2 x BandGap RefLo = Vdd/2 - BandGap Min 1.274 Vdd/2 - 0.027 Not Allowed P2[4] - 0.008 BG - 0.009 1.6 x BG - 0.018 -0.034 Not Allowed Not Allowed Not Allowed Not Allowed P2[4] + P2[6] - 0.075 Not Allowed Not Allowed P2[4] + P2[6] - 0.009 P2[4] + P2[6] + 0.057 V Typ 1.30 Vdd/2 - 0.003 P2[4] + 0.001 BG 1.6 x BG 0.000 Max 1.326 Vdd/2 + 0.002 P2[4] + 0.009 BG + 0.009 1.6 x BG + 0.018 0.034 Unit V V V V V V
Note 7. AGND tolerance includes the offsets of the local buffer in the PSoC block.
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Table 26. Silicon Revision A - 3.3V DC Analog Reference Specifications (continued) Symbol Description - RefLo = BandGap - RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) - RefLo = P2[4] - BandGap (P2[4] = Vdd/2) - RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) Min Not Allowed Not Allowed Not Allowed P2[4] - P2[6] - 0.048 P2[4] - P2[6] + 0.022 P2[4] - P2[6] + 0.092 V Typ Max Unit
Table 27. Silicon Revision B - 3.3V DC Analog Reference Specifications Symbol BG - - - - - - - - - - - - - - - - - Description Bandgap Voltage Reference AGND = Vdd/2[8] AGND = 2 x BandGap[8] AGND = P2[4] (P2[4] = Vdd/2) AGND = BandGap[8] AGND = 1.6 x BandGap[8] AGND Block to Block Variation (AGND = Vdd/2)[8] RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) RefHi = 3.2 x BandGap RefLo = Vdd/2 - BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) RefLo = P2[4] - BandGap (P2[4] = Vdd/2) RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) Min 1.28 Vdd/2 - 0.027 Not Allowed P2[4] - 0.008 BG - 0.009 1.6 x BG - 0.018 -0.034 Not Allowed Not Allowed Not Allowed Not Allowed P2[4] + P2[6] - 0.06 Not Allowed Not Allowed Not Allowed Not Allowed Not Allowed P2[4] - P2[6] - 0.048 P2[4] - P2[6] + 0.01 P2[4] - P2[6] + 0.048 V P2[4] + P2[6] - 0.01 P2[4] + P2[6] + 0.057 V Typ 1.30 Vdd/2 P2[4] BG 1.6 x BG 0.000 Max 1.32 Vdd/2 + 0.005 P2[4] + 0.009 BG + 0.009 1.6 x BG + 0.018 0.034 Unit V V V V V mV
DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 28. DC Analog PSoC Block Specifications Symbol RCT CSC Description Resistor Unit Value (Continuous Time) Capacitor Unit Value (Switch Cap) Min - - Typ 12.2 80 Max - - Unit k fF
Note 8. AGND tolerance includes the offsets of the local buffer in the PSoC block. See Application Note AN2012 "Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation" for information on trimming for operation at 3.3V.
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DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the PSoC Programmable System-on-Chip Technical Reference Manual for more information on the VLT_CR register. Table 29. DC POR and LVD Specifications Symbol VPPOR0R VPPOR1R VPPOR2R VPPOR0 VPPOR1 VPPOR2 VPH0 VPH1 VPH2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VPUMP0 VPUMP1 VPUMP2 VPUMP3 VPUMP4 VPUMP5 VPUMP6 VPUMP7 Description Vdd Value for PPOR Trip (positive ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for PPOR Trip (negative ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b PPOR Hysteresis PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Vdd Value for PUMP Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Min Typ 2.91 4.39 4.55 2.82 4.39 4.55 92 0 0 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 Max Unit V V V V V V mV mV mV V V V V V V V V V V V V V V V V V V Notes Vdd must be greater than or equal to 2.5V during startup, reset from the XRES pin, or reset from Watchdog.
-
-
-
-
- - - 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72
- - - 2.98[9] 3.08 3.20 4.08 4.57 4.74[10] 4.82 4.91
2.96 3.03 3.18 4.11 4.55 4.63 4.72 4.90
3.02 3.10 3.25 4.19 4.64 4.73 4.82 5.00
3.08 3.16 3.32 4.28 4.74 4.82 4.91 5.10
Notes 9. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply. 10. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
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DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 30. DC Programming Specifications Symbol IDDP VILP Description Min Supply Current During Programming or Verify - Input Low Voltage During Programming or - Verify VIHP Input High Voltage During Programming or 2.2 Verify IILP Input Current when Applying Vilp to P1[0] or - P1[1] During Programming or Verify IIHP Input Current when Applying Vihp to P1[0] or - P1[1] During Programming or Verify VOLV Output Low Voltage During Programming or - Verify VOHV Output High Voltage During Programming or Vdd - 1.0 Verify FlashENP Flash Endurance (per block) 50,000 FlashENT Flash Endurance (total)[11] FlashDR Flash Data Retention
B
Typ 5 - - - - - - - - -
Max 25 0.8 - 0.2 1.5 Vss + 0.75 Vdd - - -
Unit mA V V mA mA V V - - Years
Notes
Driving internal pull-down resistor. Driving internal pull-down resistor.
Erase/write cycles per block. Erase/write cycles.
1,800,0 00 10
Note 11. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information
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AC Electrical Characteristics
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 31. AC Chip-Level Specifications Symbol FIMO FCPU1 FCPU2 F48M F24M F32K1 F32K2 FPLL Description Internal Main Oscillator Frequency CPU Frequency (5V Nominal) CPU Frequency (3.3V Nominal) Digital PSoC Block Frequency Digital PSoC Block Frequency Internal Low Speed Oscillator Frequency External Crystal Oscillator PLL Frequency Min 23.4 0.93 0.93 0 0 15 - - - 0.5 0.5 - - Typ 24 24 12 48 24 32 32.768 23.986 - - - 1700 2800 Max 24.6[12] 24.6[12,13] 12.3[13,14] 49.2[12,13, 15] 24.6[13, 15] 64 - - 600 10 50 2620 3800 Unit MHz MHz MHz MHz MHz kHz kHz MHz ps ms ms ms ms Notes Trimmed. Utilizing factory trim values. Trimmed. Utilizing factory trim values. Trimmed. Utilizing factory trim values. Refer to the AC Digital Block Specifications below.
Accuracy is capacitor and crystal dependent. 50% duty cycle. Multiple (x732) of crystal frequency.
Jitter24M2 24 MHz Period Jitter (PLL) TPLLSLEW PLL Lock Time TPLLSLEWS PLL Lock Time for Low Gain Setting
LOW
TOS TOSACC
External Crystal Oscillator Startup to 1% External Crystal Oscillator Startup to 100 ppm
The crystal oscillator frequency is within 100 ppm of its final value by the end of the Tosacc period. Correct operation assumes a properly loaded 1 W maximum drive level 32.768 kHz crystal. 3.0V Vdd 5.5V, -40C TA 85C.
Jitter32k TXRST DC24M Step24M Fout48M Jitter24M1 FMAX TRAMP
32 kHz Period Jitter External Reset Pulse Width 24 MHz Duty Cycle 24 MHz Trim Step Size 48 MHz Output Frequency 24 MHz Period Jitter (IMO) Maximum frequency of signal on row input or row output. Supply Ramp Time
- 10 40 - 46.8 - - 0
100 - 50 50 48.0 600 - -
- 60 - 49.2[12,14]
ns s % kHz MHz ps MHz s
Trimmed. Utilizing factory trim values.
12.3 -
Notes 12. 4.75V < Vdd < 5.25V. 13. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. 14. 3.0V < Vdd < 3.6V. See Application Note AN2012 "Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation" for information on trimming for operation at 3.3V. 15. See the individual user module data sheets for information on maximum frequencies for user modules.
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Figure 12. PLL Lock Timing Diagram
PLL Enable
TPLLSLEW 24 MHz
FPLL PLL Gain
0
Figure 13. PLL Lock for Low Gain Setting Timing Diagram
PLL Enable
TPLLSLEWLOW 24 MHz
FPLL PLL Gain
1
Figure 14. External Crystal Oscillator Startup Timing Diagram
32K Select
TOS 32 kHz
F32K2
Figure 15. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1
F 24M
Figure 16. 32 kHz Period Jitter (ECO) Timing Diagram
Jitter32k
F 32K2
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AC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 32. AC GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF Min 0 3 2 10 10 Typ - - - 27 22 Max 12 18 18 - - Unit MHz ns ns ns ns Notes Normal Strong Mode Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90%
Figure 17. GPIO Timing Diagram
90% GPIO Pin Output Voltage 10%
TRiseF TRiseS
TFallF TFallS
AC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block. Power = High and Opamp Bias = High is not supported at 3.3V. Table 33. 5V AC Operational Amplifier Specifications Symbol TROA Description Rising Settling Time from 80% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Falling Settling Time from 20% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Min Typ Max Unit s s s s s s V/s V/s V/s V/s V/s V/s
- - -
- - -
3.9 0.72 0.62
TSOA
- - - 0.15 1.7 6.5 0.01 0.5 4.0
- - - - - - - - -
5.9 0.92 0.72 - - - - - -
SRROA
SRFOA
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Table 33. 5V AC Operational Amplifier Specifications (continued) Symbol BWOA Description Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Noise at 1 kHz (Power = Medium, Opamp Bias = High) Min 0.75 3.1 5.4 - Typ - - - 100 Max - - - - Unit MHz MHz MHz nV/rt-Hz
ENOA
Table 34. 3.3V AC Operational Amplifier Specifications Symbol Description Rising Settling Time from 80% of V to 0.1% of V (10 pF load, Unity Gain) TROA Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High TSOA Falling Settling Time from 20% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Noise at 1 kHz (Power = Medium, Opamp Bias = High) Min Typ Max Units s s s s V/s V/s V/s V/s MHz MHz nV/rt-Hz
- -
- -
3.92 0.72
- - 0.31 2.7 0.24 1.8 0.67 2.8 -
- - - - - - - - 100
5.41 0.72 - - - - - - -
SRROA SRFOA BWOA ENOA
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor. Figure 18. Typical AGND Noise with P2[4] Bypass
dBV/rtHz 10000
0 0.01 0.1 1.0 10
1000
100 0.001
0.01
0.1 Freq (kHz)
1
10
100
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level.
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Figure 19. Typical Opamp Noise
nV/rtHz 10000 PH_BH PH_BL PM_BL PL_BL 1000
100
10 0.001
0.01
0.1
Freq (kHz)
1
10
100
AC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V at 25C and are for design guidance only. Table 35. AC Low Power Comparator Specifications Symbol TRLPC Description LPC response time Min - Typ - Max 50 Unit s Notes 50 mV overdrive comparator reference set within VREFLPC.
AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 36. AC Digital Block Specifications Function Description Min Typ Max 49.2 24.6 50[16] - - 50[16] - - - - - - - - - 49.2 24.6 - 49.2 24.6 ns MHz MHz ns MHz MHz 4.75V < Vdd < 5.25V 4.75V < Vdd < 5.25V Unit Notes 4.75V < Vdd < 5.25V 3.0V < Vdd < 4.75V All Maximum Block Clocking Frequency (> 4.75V) Functions Maximum Block Clocking Frequency (< 4.75V) Timer Capture Pulse Width Maximum Frequency, No Capture Maximum Frequency, With Capture Counter Enable Pulse Width Maximum Frequency, No Enable Input Maximum Frequency, Enable Input
Notes 16. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). 17. Refer to Table 47 on page 50
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Table 36. AC Digital Block Specifications (continued) Function Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS Maximum Input Clock Frequency (PRS Mode) CRCPRS Maximum Input Clock Frequency (CRC Mode) SPIM SPIS Transmitter Maximum Input Clock Frequency Maximum Input Clock Frequency Width of SS_ Negated Between Transmissions Maximum Input Clock Frequency [16] Silicon A Silicon B Silicon B Maximum Input Clock Frequency with Vdd 4.75V, 2 Stop Bits Receiver Maximum Input Clock Frequency [17] Silicon A Silicon B Silicon B Maximum Input Clock Frequency with Vdd 4.75V, 2 Stop Bits 20 50[16] 50[16] - - - - - - - - - - 49.2 49.2 ns ns ns MHz MHz 4.75V < Vdd < 5.25V 4.75V < Vdd < 5.25V Description Min Typ Max Unit Notes
-
-
24.6
MHz
- - 50[16] - - -
- - - - - -
8.2 4.1 - 16.4 24.6 49.2
MHz MHz MHz MHz MHz MHz
Maximum data rate at 4.1 MHz due to 2 x over clocking.
Maximum data rate at 2.05 MHz due to 8 x over clocking. Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 6.15 MHz due to 8 x over clocking. Maximum data rate at 2.05 MHz due to 8 x over clocking. Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 6.15 MHz due to 8 x over clocking.
- - -
- - -
16.4 24.6 49.2
MHz MHz MHz
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AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 37. 5V AC Analog Output Buffer Specifications Symbol TROB TSOB SRROB SRFOB BWOB BWOB Description Rising Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High Falling Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load Power = Low Power = High Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load Power = Low Power = High Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load Power = Low Power = High Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load Power = Low Power = High Min - - - - 0.65 0.65 0.65 0.65 0.8 0.8 300 300 Typ - - - - - - - - - - - - Max 2.5 2.5 2.2 2.2 - - - - - - - - Unit s s s s V/s V/s V/s V/s MHz MHz kHz kHz
Table 38. 3.3V AC Analog Output Buffer Specifications Symbol TROB TSOB SRROB SRFOB BWOB BWOB Description Rising Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High Falling Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load Power = Low Power = High Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load Power = Low Power = High Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load Power = Low Power = High Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load Power = Low Power = High Min - - - - 0.5 0.5 0.5 0.5 0.7 0.7 200 200 Typ - - - - - - - - - - - - Max 3.8 3.8 2.6 2.6 - - - - - - - - Unit s s s s V/s V/s V/s V/s MHz MHz kHz kHz
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AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 39. 5V AC External Clock Specifications Symbol FOSCEXT - - - Frequency High Period Low Period Power Up IMO to Switch Description Min 0.093 20.6 20.6 150 Typ - - - - Max 24.6 5300 - - Unit MHz ns ns s
Table 40. 3.3V AC External Clock Specifications Symbol FOSCEXT FOSCEXT - - - Description Frequency with CPU Clock divide by 1[18] Frequency with CPU Clock divide by 2 or greater[19] High Period with CPU Clock divide by 1 Low Period with CPU Clock divide by 1 Power Up IMO to Switch Min 0.093 0.186 41.7 41.7 150 Typ - - - - - Max 12.3 24.6 5300 - - Unit MHz MHz ns ns s
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 41. AC Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3 Description Rise Time of SCLK Fall Time of SCLK Data Set up Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK Min 1 1 40 40 0 - - - - Typ - - - - - 10 10 - - Max 20 20 - - 8 - - 45 50 Unit ns ns ns ns MHz ms ms ns ns Notes
Vdd > 3.6 3.0 Vdd 3.6
Notes 18. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. 19. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent duty cycle requirement is met.
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AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 42. AC Characteristics of the I2C SDA and SCL Pins Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C Description SCL Clock Frequency Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Set-up Time for a Repeated START Condition Data Hold Time Data Set-up Time Set-up Time for STOP Condition Bus Free Time Between a STOP and START Condition Pulse Width of spikes are suppressed by the input filter. Standard Mode Min Max 0 100 4.0 - 4.7 4.0 4.7 0 250 4.0 4.7 - - - - - - - - - Fast Mode Min Max 0 400 0.6 - 1.3 0.6 0.6 0 100[20] 0.6 1.3 0 - - - - - - - 50 Unit kHz s s s s s ns s s ns
Figure 20. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA
TLOWI2C
TSUDATI2C
THDSTAI2C
TSPI2C
TBUFI2C
SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C Sr TSUSTOI2C P S
Note 20. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
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Packaging Information
This section illustrates the packaging specifications for the CY8C27x43 PSoC device, along with the thermal impedances for each package and the typical package capacitance on crystal pins. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/design/MR10161.
Packaging Dimensions
Figure 21. 8-Pin (300-Mil) PDIP
51-85075 *A
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Figure 22. 20-Pin (210-Mil) SSOP
51-85077 *C
Figure 23. 20-Pin (300-Mil) Molded SOIC
51-85024 *C
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Figure 24. 28-Pin (300-Mil) Molded DIP
51-85014 *D
Figure 25. 28-Pin (210-Mil) SSOP
51-85079 *C
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Figure 26. 28-Pin (300-Mil) Molded SOIC
51-85026 *D
Figure 27. 44-Pin TQFP
51-85064 *C
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Figure 28. 48-Pin (300-Mil) SSOP
51-85061 *C 51-85061-C
Figure 29. 48-Pin QFN 7X7X 0.90 MM (Sawn Type)
001-13191 *C
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Figure 30. 48-Pin (7x7 mm) QFN
51-85152 *C
Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
Thermal Impedances
Table 43. Thermal Impedances per Package Package 8 PDIP 20 SSOP 20 SOIC 28 PDIP 28 SSOP 28 SOIC 44 TQFP 48 SSOP 48 QFN
* TJ = TA + POWER x JA
Capacitance on Crystal Pins
Table 44. Typical Package Capacitance on Crystal Pins Package 8 PDIP 20 SSOP 20 SOIC 28 PDIP 28 SSOP 28 SOIC 44 TQFP 48 SSOP 48 QFN Package Capacitance 2.8 pF 2.6 pF 2.5 pF 3.5 pF 2.8 pF 2.7 pF 2.6 pF 3.3 pF 2.3 pF Typical JA * 120 oC/W 116 67 68 69
oC/W oC/W oC/W oC/W
79 oC/W 95 oC/W 61 oC/W 18 oC/W
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Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability. Table 45. Solder Reflow Peak Temperature Silicon A* Package 8 PDIP 20 SSOP 20 SOIC 28 PDIP 28 SSOP 28 SOIC 44 TQFP 48 SSOP 48 QFN Minimum Peak Temperature** 220oC 220oC 220oC 220oC 220oC 220oC 220oC 220oC 220oC Maximum Peak Temperature 240oC 240oC 240oC 240oC 240oC 240oC 240oC 240oC 240oC Silicon B* Minimum Peak Temperature* 240oC 240oC 220oC 240oC 240oC 220oC 220oC 220oC 240oC Maximum Peak Temperature 260oC 260oC 260oC 260oC 260oC 260oC 260oC 260oC 260oC
*Refer to Table 47 on page 50. **Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 5oC with Sn-Pb or 245 5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.
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Development Tool Selection
This chapter presents the development tools available for all current PSoC device families including the CY8C27x43 family.

iMAGEcraft C Compiler (Registration Required) ISSP Cable USB 2.0 Cable and Blue Cat-5 Cable 2 CY8C29466-24PXI 28-PDIP Chip Samples
Software
PSoC DesignerTM At the core of the PSoC development software suite is PSoC Designer. Utilized by thousands of PSoC developers, this robust software has been facilitating PSoC designs for half a decade. PSoC Designer is available free of charge at http://www.cypress.com under DESIGN RESOURCES >> Software and Drivers. PSoC Programmer Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer or PSoC Express. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free ofcharge at http://www.cypress.com/psocprogrammer. CY3202-C iMAGEcraft C Compiler CY3202 is the optional upgrade to PSoC Designer that enables the iMAGEcraft C compiler. It can be purchased from the Cypress Online Store. At http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items.
CY3210-ExpressDK PSoC Express Development Kit The CY3210-ExpressDK is for advanced prototyping and development with PSoC Express (may be used with ICE-Cube In-Circuit Emulator). It provides access to I2C buses, voltage reference, switches, upgradeable modules and more. The kit includes:

PSoC Express Software CD Express Development Board 4 Fan Modules 2 Proto Modules MiniProg In-System Serial Programmer MiniEval PCB Evaluation Board Jumper Wire Kit USB 2.0 Cable Serial Cable (DB9) 110 ~ 240V Power Supply, Euro-Plug Adapter 2 CY8C24423A-24PXI 28-PDIP Chip Samples 2 CY8C27443-24PXI 28-PDIP Chip Samples 2 CY8C29466-24PXI 28-PDIP Chip Samples
Development Kits
All development kits can be purchased from the Cypress Online Store. CY3215-DK Basic Development Kit The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface allows users to run, halt, and single step the processor and view the content of specific memory locations. Advance emulation features also supported through PSoC Designer. The kit includes:

Evaluation Tools
All evaluation tools can be purchased from the Cypress Online Store. CY3210-MiniProg1 The CY3210-MiniProg1 kit allows a user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes:

PSoC Designer Software CD ICE-Cube In-Circuit Emulator ICE Flex-Pod for CY8C29x66 Family Cat-5 Adapter Mini-Eval Programming Board 110 ~ 240V Power Supply, Euro-Plug Adapter
MiniProg Programming Unit MiniEval Socket Programming and Evaluation Board 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample PSoC Designer Software CD Getting Started Guide USB 2.0 Cable
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Device Programmers
All device programmers can be purchased from the Cypress Online Store. CY3216 Modular Programmer The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes:

CY3210-PSoCEval1 The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes:

Evaluation Board with LCD Module MiniProg Programming Unit 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2) PSoC Designer Software CD Getting Started Guide USB 2.0 Cable
Modular Programmer Base 3 Programming Module Cards MiniProg Programming Unit PSoC Designer Software CD Getting Started Guide USB 2.0 Cable
CY3214-PSoCEvalUSB The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LFXI PSoC device. Special features of the board include both USB and capacitive sensing development and debugging support. This evaluation board also includes an LCD module, potentiometer, LEDs, an enunciator and plenty of bread boarding space to meet all of your evaluation needs. The kit includes:

CY3207ISSP In-System Serial Programmer (ISSP) The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment. Note: CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes:

PSoCEvalUSB Board LCD Module MIniProg Programming Unit Mini USB Cable PSoC Designer and Example Projects CD Getting Started Guide Wire Pack
CY3207 Programmer Unit PSoC ISSP Software CD 110 ~ 240V Power Supply, Euro-Plug Adapter USB 2.0 Cable
Accessories (Emulation and Programming)
Table 46. Emulation and Programming Accessories Part # CY8C27143-24PXI CY8C27243-24PVXI CY8C27243-24SXI CY8C27443-24PXI CY8C27443-24PVXI CY8C27443-24SXI CY8C27543-24AXI CY8C27643-24PVXI CY8C27643-24LFXI Pin Package 8 PDIP 20 SSOP 20 SOIC 28 PDIP 28 SSOP 28 SOIC 44 TQFP 48 SSOP 48 QFN Flex-Pod Kit[21] CY3250-27XXX CY3250-27XXX CY3250-27XXX CY3250-27XXX CY3250-27XXX CY3250-27XXX CY3250-27XXX CY3250-27XXX CY3250-27XXXQFN Foot Kit[22] CY3250-8PDIP-FK CY3250-20SSOP-FK CY3250-20SOIC-FK CY3250-28PDIP-FK CY3250-28SSOP-FK CY3250-28SOIC-FK CY3250-44TQFP-FK CY3250-48SSOP-FK CY3250-48QFN-FK Adapter[23] Adapters can be found at http://www.emulation.com.
Notes 21. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods. 22. Foot kit includes surface mount feet that can be soldered to the target PCB. 23. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at http://www.emulation.com.
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3rd-Party Tools
Several tools have been specially designed by the following 3rd-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools can be found at http://www.cypress.com under DESIGN RESOURCES >> Evaluation Boards.
Build a PSoC Emulator into Your Board
For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device, see Application Note "Debugging - Build a PSoC Emulator into Your Board AN2323" at http://www.cypress.com/an2323.
Ordering Information
The following table lists the CY8C27x43 PSoC device's key package features and ordering codes. Table 47. CY8C27x43 PSoC Device Key Features and Ordering Information
Analog Blocks (Columns of 3) Digital Blocks (Rows of 4) Switch Mode Pump Temperature Range XRES Pin No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes Yes Yes Digital IO Pins Ordering Code Package Analog Outputs 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Analog Inputs 4 8 8 8 8 12 12 12 12 12 12 12 12 12 12 12 14 4 8 8 8 8 12 12 12 Flash (Bytes) 16K 16K 16K 16K 16K 16K 16K 16K 16K 16K 16K 16K 16K 16K 16K 16K 16K 16K 16K 16K 16K 16K 16K 16K 16K RAM (Bytes) 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256
CY8C27x43 Silicon B - These parts are lead free and offer the following improvements. The DEC_CR1 register selections are enhanced to allow any digital block to be the decimator clock source, the ECO EX and ECO EXW bits in the CPU_SCR1 register are readable, and the accuracy of the analog reference is enhanced (see the Electrical Specifications chapter). All silicon A errata are fixed in silicon B. 8 Pin (300 Mil) DIP 20 Pin (210 Mil) SSOP 20 Pin (210 Mil) SSOP (Tape and Reel) 20 Pin (300 Mil) SOIC 20 Pin 300 Mil) SOIC (Tape and Reel) 28 Pin (300 Mil) DIP 28 Pin (210 Mil) SSOP 28 Pin (210 Mil) SSOP (Tape and Reel) 28 Pin (300 Mil) SOIC 28 Pin (300 Mil) SOIC (Tape and Reel) 44 Pin TQFP 44 Pin TQFP (Tape and Reel) 48 Pin (300 Mil) SSOP 48 Pin (300 Mil) SSOP (Tape and Reel) 48 Pin (7x7) QFN 48 Pin (7x7) QFN (Tape and Reel) 56 Pin OCD SSOP 8 Pin (300 Mil) DIP 20 Pin (210 Mil) SSOP 20 Pin (210 Mil) SSOP (Tape and Reel) 20 Pin (300 Mil) SOIC 20 Pin 300 Mil) SOIC (Tape and Reel) 28 Pin (300 Mil) DIP 28 Pin (210 Mil) SSOP 28 Pin (210 Mil) SSOP (Tape and Reel) CY8C27143-24PXI CY8C27243-24PVXI CY8C27243-24PVXIT CY8C27243-24SXI CY8C27243-24SXIT CY8C27443-24PXI CY8C27443-24PVXI CY8C27443-24PVXIT CY8C27443-24SXI CY8C27443-24SXIT CY8C27543-24AXI CY8C27543-24AXIT CY8C27643-24PVXI CY8C27643-24PVXIT CY8C27643-24LFXI CY8C27643-24LFXIT CY8C27002-24PVXI[24] CY8C27143-24PI CY8C27243-24PVI CY8C27243-24PVIT CY8C27243-24SI CY8C27243-24SIT CY8C27443-24PI CY8C27443-24PVI CY8C27443-24PVIT No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes Yes Yes -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 6 16 16 16 16 24 24 24 24 24 40 40 44 44 44 44 44 6 16 16 16 16 24 24 24
CY8C27x43 Silicon A - Silicon A is not recommended for new designs.
Note 24. This part may be used for in-circuit debugging. It is NOT available for production.
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Table 47. CY8C27x43 PSoC Device Key Features and Ordering Information (continued)
Analog Blocks (Columns of 3) Digital Blocks (Rows of 4) Switch Mode Pump Temperature Range XRES Pin Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Digital IO Pins Ordering Code Package Analog Outputs 4 4 4 4 4 4 4 4 4 4 Flash (Bytes) Analog Inputs 12 12 12 12 12 12 12 12 12 12 RAM (Bytes) 256 256 256 256 256 256 256 256 256 256
28 Pin (300 Mil) SOIC 28 Pin (300 Mil) SOIC (Tape and Reel) 44 Pin TQFP 44 Pin TQFP (Tape and Reel) 48 Pin (300 Mil) SSOP 48 Pin (300 Mil) SSOP (Tape and Reel) 48 Pin (7x7) MLF 48 Pin (7x7) MLF (Tape and Reel) 48 Pin (7X7X 0.90 MM) QFN (Sawn) 48 Pin (7X7X 0.90 MM) QFN (Sawn)
CY8C27443-24SI CY8C27443-24SIT CY8C27543-24AI CY8C27543-24AIT CY8C27643-24PVI CY8C27643-24PVIT CY8C27643-24LFI CY8C27643-24LFIT CY8C27643-24LTXI CY8C27643-24LTXIT
16K 16K 16K 16K 16K 16K 16K 16K 16K 16K
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
-40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
8 8 8 8 8 8 8 8 8 8
12 12 12 12 12 12 12 12 12 12
24 24 40 40 44 44 44 44 44 44
Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).
Ordering Code Definitions
CY 8 C 27 xxx-SPxx
Package Type: PX = PDIP Pb-Free SX = SOIC Pb-Free PVX = SSOP Pb-Free LFX/LKX = QFN Pb-Free AX = TQFP Pb-Free Speed: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress Thermal Rating: C = Commercial I = Industrial E = Extended
Document Number: 38-12012 Rev. *M
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Document History Page
Document Title: CY8C27143, CY8C27243, CY8C27443, CY8C27543, CY8C27643 PSoC(R) Programmable System-on-ChipTM Document Number: 38-12012 Revision ECN No. Submission Date ** *A *B *C *D *E *F *G *H 127087 128780 128992 129283 129442 130129 130651 131298 229416 7/01/2003 7/29/2003 8/14/2003 8/28/2003 9/09/2003 10/13/2003 10/28/2003 11/18/2003 See ECN Origin of Change New Silicon. Description of Change New document (Revision **).
Engineering and New electrical spec additions, fix of Core Architecture links, corrections to NWJ. some text, tables, drawings, and format. NWJ NWJ NWJ NWJ NWJ NWJ SFV Interrupt controller table fixed, refinements to Electrical Spec section and Register chapter. Significant changes to the Electrical Specifications section. Changes made to Electrical Spec section. Added 20/28-Lead SOIC packages and pinouts. Revised document for Silicon Revision A. Refinements to Electrical Specification section and I2C chapter. Revisions to GDI, RDI, and Digital Block chapters. Revisions to AC Digital Block Spec and miscellaneous register changes. New data sheet format and organization. Reference the PSoC Programmable System-on-Chip Technical Reference Manual for additional information. Title change. Added Silicon B information to this data sheet. Add DS standards, update device table, swap 48-pin SSOP 45 and 46, add Reflow Peak Temp. table. Add new color and logo. Re-add pinout ISSP notation. Add URL to preferred dimensions for mounting MLF packages. Update Transmitter and Receiver AC Digital Block Electrical Specifications. Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Add new Dev. Tool section. Add CY8C20x34 to PSoC Device Characteristics table. Add OCD pinout and package diagram. Add ISSP note to pinout tables. Update package diagram revisions. Update typical and recommended Storage Temperature per industrial specs. Update CY branding and QFN convention. Update copyright and trademarks. Added note to DC Analog Reference Specification table and Ordering Information. Changed title from " CY8C27143, CY8C27243, CY8C27443, CY8C27543, and CY8C27643 PSoC Mixed Signal Array Final Data Sheet" to "CY8C27143, CY8C27243, CY8C27443, CY8C27543, CY8C27643 PSoC(R) Programmable System-on-ChipTM". Updated data sheet template. Added 48-Pin QFN (Sawn) package outline diagram and Ordering information details for CY8C27643-24LTXI and CY8C27643-24LTXIT parts
*I *J
247529 355555
See ECN See ECN
SFV HMT
*K
523233
See ECN
HMT
*L *M
2545030 2696188
07/29/08 04/22/2009
YARA DPT/PYRS
Document Number: 38-12012 Rev. *M
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.
Products
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General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb
(c) Cypress Semiconductor Corporation, 2003-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-12012 Rev. *M
Revised April 17, 2009
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PSoC DesignerTM and Programmable System-on-ChipTM are trademarks and PSoC(R) is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
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